The present invention relates to a circuit arrangement of highly integrated chips, particularly of the type produced according to the MOS technique, for microprogrammed data processing devices including an arithmetic and control unit (RSE), one or a plurality of read-only memories (ROM's), one or a plurality of random access memories (RAM's), and connecting contacts for peripheral units as well as a bus connecting the chips together.
When circuit arrangements are constituted by chips, there arises the necessity of providing connecting contacts in the numbers required for connecting further circuit components, for example further chips and peripheral devices. Since the small surface area of the chips is to be utilized as much as possible for the circuit arrangements themselves, so that little space remains for the conductor channels connected to the connecting contacts, and since only a limited number of connecting contacts can be accommodated on the relatively very small chips, there exist considerable difficulties in producing the required number of connecting contacts.
In the prior art, circuit components such as, for example, ROM's or RAM's are arranged on chips and the attainable number of connecting contacts is divided among a collecting line, or bus, in the case of modular design, peripheral output contacts, e.g., to printers or indicator devices, and peripheral input contacts, e.g., from a keyboard. If such chips were intended to be used for different types of circuit arrangements, it would inevitably occur that at one time there would be too many inputs provided by the peripheral contacts while the number of outputs would be sufficient, and at another time the reverse would be the case.
Thus, every time a circuit arrangement of the above-mentioned type was designed for a different use there arose the problem of how to utilize the chips and accomplish the intended task with the small number of connecting contacts.